1. Technical Field
The inventive concept relates to a method of fabricating a semiconductor memory, and more particularly, to a semiconductor memory device having cell patterns formed on an interconnection and a fabrication method thereof.
2. Related Art
In general, fabrication processes for a cell area, a core area and a peripheral area in a memory device are separately performed. However, the cell area, the core area and the peripheral area operate correlatively with each other. Accordingly, a structure of patterns and stacks should be formed to ensure operational and characteristic connections between correlated circuits in the cell area, the core area, and the peripheral area.
FIG. 1 is a cross-sectional view illustrating a structure of a semiconductor memory device, for example, a phase-change random access device (PCRAM).
An isolation layer 103 is formed on a semiconductor substrate 101 where a cell area, a core area, and a peripheral area are respectively defined. A switch 105 configured to select a word line is formed on the cell and core areas of the semiconductor substrate 101. At this time, a circuit pattern is also formed in the peripheral area to match the height of patterns or structures between the cell and core areas and the peripheral area.
A conductive line 107 is formed on the semiconductor substrate having the switch 105. The conductive line 107 may be formed using a metal material such as tungsten (W) and serve as a word line in a cell operation. The conductive line 107 in the cell and core areas is electrically connected to the switch 105 which is formed below the conductive line 107. The conductive line 107 in the peripheral area may contact with the underlying circuit pattern to serve as an interconnection.
A cell pattern is formed on the conductive line 107 in the cell and core areas. In particular, in the PCRAM device, the cell pattern is coupled to the conductive line 107 through an access element such as a diode.
The diode as the access element may include a barrier metal layer 109 and an N-type semiconductor layer 111; and further include a silicide layer, which could be formed by silicidation to a surface of the N-type semiconductor layer 111, to reduce a contact resistance. However, the diode is not limited thereto. In addition, a lower electrode 115, a phase-change material pattern 117, an upper electrode 119, and a bit line 121 are formed on the access element 109 and 111 (or 113) through general processes well known to one skilled in the art.
FIG. 2 is a layout of the semiconductor memory device illustrated in FIG. 1.
FIG. 2 illustrates that a plurality of unit memory cells MC are formed in a cell area, a word line contact WC is formed in a core area. Further, a contact for connection between a peripheral circuit and the cell area is formed in the peripheral area.
The unit memory cell of the memory device should have a size to guarantee an operational characteristic thereof. However, as the semiconductor device is highly integrated, a word line size (or width), that is, a critical dimension of the conductive line 107, decreases so that the series resistance of the conductive line 107 increases. The increased series resistance of the conduction line 107 cause voltage drop, thereby threatening a sensing margin.
To solve above-described concerns, the word line selection switch 105 should be designed to provide sufficient driving current on the conductive line 107. However, a large transistor is required to increase drivability of the switch 105, resulting in increase of a chip size.
As another method to solve the concerns, a method of forming a deep trench for the conductive line 107 may be considered. However, the method may be difficult to be applied because of restriction based on integration degree of the semiconductor memory device.